During his March 10th keynote at Magma’s MUSIC users conference in Silicon Valley, CEO Rajeev Madhavan left the distinct impression that analog IP is now a reality.
I had never heard it stated with such conviction, however, and the question was already on the list for the Mocha Mystery Series – so Madhavan agreed to speak by phone at a later point to discuss analog IP in greater detail. His comments from our April 15th phone call are below.
Before reading further, note there will be major announcements made at DAC in this area, with particular news out of the manufacturing sector.
Note also that Madhavan co-founded Magma in 1997, and has served as President, CEO, and Chairman of the Board. Prior to Magma, he co-founded Ambit Design and LogicVision. His MSEE is from Queen’s University in Ontario.
Q – Is there such a thing as analog IP?
Rajeev Madhavan – Historically, there has been no analog IP that you could preserve in any form, and optimize for a particular node.
For instance, if you designed an HDMI at 90 nanometers, you started from scratch. For an analog-to-digital converter, you had to simulate everything in the design. If you went to a specialized analog foundry to use their low power process, it took months and months to get it done.
[That’s why] analog IP has always been more about services, and less about IP. It’s been about telling the customer, “I’ve done this before.”
You’ve entered a customer account with, “I’ve got this technology and these IP blocks, but it’s my services built around my experience with certain types of IP that you are buying.”
All of that is about to change, however. We’ve added algorithms and techniques, [and achieved] the most exciting thing I’ve done in my EDA life in terms of technology!
It’s actually working, and [in cooperation] with one of the top foundry companies, it will be announced at DAC!
Now analog IP can be used as building blocks of design, with given optimizations at certain nodes. Plus, it will be migratable! Now it can be optimized to give better performance, rather than tweaking the design for years [to get it right].
And, there’s actually a layout tool that’s [at a development point comparable] to where we were with digital many years ago
Synopsys realized early on, that you needed some base cells in digital, so they created a digital IP business over 15 years ago. The first IP element was the adder/multiplier – the kind of things that come along in a library, and then get picked by the tool for optimization. Now we’ve actually done the same thing in analog.
It took a long time to understand the customers’’ needs, and to get the tool for automation, but we’ve got it in deployment in 12 of the top 20 semiconductor companies now.
We are really breaking new ground here, which for me is the final frontier of design. We are actually allowing the analog designers to think in terms of band gaps, not transistors, and allowing for more repeated reuse – telling the customer that if they’re doing a design at 180 nanometers, they can do it at 90 nanometers, as well.
It’s a very unique value proposition, and we’re all very excited about it! To succeed [in the long run], we know we need to create a portfolio of analog IP companies around us. We are working with a lot of companies to do that.
There are two tactics available. We can keep the technology to ourselves, or we can allow everyone else to create their own IP using the technology. I am very much in favor of the second approach, creating a business model that allows people to innovate.
Q – So, analog IP isn't the question? Instead it’s about being able to migrate an analog design block from one process node to the next smaller node?
Rajeev Madhavan – If you look at a PLL with 10-to-20 sub-blocks – when you go from one process to another, you have to make changes. But if you make those changes and optimize it using the tool, that will allow you to meet new specs.
The problem has always been there, to come up with a solution for resizing the design, with the analog part always inherently more complex, because it’s not a discrete model like in digital. In analog, it’s about working with a continuous algorithm, one that can be scaled to any dimension. Mathematically, it’s very complex.
You have to put your digital experience aside, and allow for a heuristic solution – one that converges. This continuous optimization problem can only be solved by providing the user with a tool that can input the heuristics into an automated solution – a very unique thing.
Q – Fundamentally, it’s a math problem?
Rajeev Madhavan – Yes, it’s a tricky, but beautiful math problem, with lots of good things coming out [of the solution].
Everything has to be done to maintain electrical integrity in the design, no matter what is changed. Previously, designers used design rules to hit the mark, but now the problem has been formulated at the math level. The algorithms solve it at the math level, rather the engineer [having to do it].
Q – So, it’s the layout tool that’s been lacking?
Rajeev Madhavan – Absolutely, just like in digital design in the early days. The difference is that this optimization will now happen at the system level.
[To reiterate], in RTL synthesis, the circuit is being done by the tool. People have tried to solve the analog problem by doing exactly the same thing, but it has not worked.
It’s forced us to accept the fact that analog designers are among the most ingenious people, which is what has keeps them alive professionally and differentiated. They are experts at optimizing for a give process, at doing layout for a given problem.
Q – But isn’t the problem creating analog IP, not the initial design?
Rajeev Madhavan – Absolutely, but this is about re-purposing designs. It’s about generating 10 to 15 different types of circuits, and exploring an entire design space at different voltages, rather than just generating one circuit. We’ve achieved this, and also solved the layout. The solution would not have been complete without both.
Q – Now you‘ve got a tool, how do you get the analog guys to use it?
Rajeev Madhavan – With 12 out of the top 20 semis using the tool, we’re seeing very good proliferation with engineers learning how to use it. However, we’re not replacing the humans. The analog designer is still the god of circuit topology!
We’re not attacking the designers, but providing somet'g that can be integrated into their Cadence lay-out environment. The tool just allows them to work more efficiently. If you accept Moore’s Law in analog, the designers need to be able to make changes automatically [as the process nodes shrink].
Q – I recently heard an vendor bragging that they have over 3000 available IP blocks? How much of that do you think is analog IP?
Rajeev Madhavan – You don’t need 3000 different types of IP in analog. You only need about 100 baseline categories.
But, if you need to make changes in those blocks, the customization capabilities have to be a lot greater than in digital IP blocks.
[However the number of IP blocks is not the point], it’s that when people talk about the quality of IP, they won’t just be talking about digital IP. They will be talking about analog IP, as well.
I have no doubt about this!