EDA Confidential ...

Bob Patti: 3D @ Tezzaron

by Peggy Aycinena

December 16, 2010  

Bob Patti, CTO at Tezzaron, gave the keynote in the spring at the March 10th Magma MUSIC Users Group meeting in Silicon Valley. Patti's talk was an impressive tutorial-type overview of the issues related to 3D design.

Fast forward 8 months to November 10th at ICCAD 2010, also in Silicon Valley, and the half-day special session on 3D manufacturing. Penn State EECS Professor Yuan Xie led the afternoon with his 30-minute presentation, also a high-level overview of issues related to 3D.

In the course of his talk, Xie noted the market drivers for 3D stacking include improved electrical performance due to a smaller chip footprint and faster interconnects/higher bandwidths, and posed one question, Can 3D be cheaper than technology scaling? – and mentioned one company, Tezzaron.

Happily, I already had the following interview with Tezzaron's CTO in the can, so I knew Tezzaron's Bob Patti had the answer to Xie's question.


Tezzaron CTO Bob Patti ...

Bob Patti's not only a knowledgeable and articulate spokesman for All Things 3D, he's also Been there, Done that, because Tezzaron is a real, living, breathing corporate entity that's doing 3D. They're not just hypothesizing – they're really doing it – so my conversation with Bob started with his thumbnail sketch of the ramping up of the technology.

Bob said, “The industry's made incredible progress over the last 10 years. Ten years ago, people said there was no reason [to go 3D], and that it would never work.

“Then, 3 years ago it started to gain somewhat of an audience, because people were seeing a foreshadowing of problems with scaling, and believed 3D would offer an easier road. Since then, it's picked up a fair amount of momentum. My perception now is that virtually any semiconductor company in the world will say they've got something in this area that they're working on, or partnering on, or at least studying.”

I relayed to Bob a comment I'd heard on the 3D panel at DAC this past June in Anaheim: The big players will undercut the 3D market by lowering their prices.

Bob said, “I don't believe that, because 3D is orthogonal to all other technologies. It enhances standard semiconductor technology, whether it's .5 micron or 28 nanometers, so I don't see any possibility of undercutting the growth in 3D.

“[Besides], a lot of the advantages you get out of 3D are not price-based. There is some cost reduction, but the big gain is in performance improvement, and you can't get that by manipulating the market. And, fundamentally, 3D is an inexpensive technology to practice.

“Consider this. If you could build a high-volume facility that did nothing but 3D integration in the tens of thousands of wafers a month, an $80 million to $100 million investment would produce the same yield as $2 billion spent on a 28-nanometer fab. That's why doing 3D is a 1.5 order of magnitude smaller cost [than building a smaller-node fab]. So the 'big guys' won't be driving 3D out of the marketplace – or even stalling it, for that matter!”

Bob added, “There are some things – various hurdles – that will slow adoption, but I don't perceive it to be at all possible for industry players to do that.”

And what are those hurdles? Bob answered, “I can tell you, we've had working functional parts for more than 6 years. The technical hurdles are a lot less daunting than the business hurdles.”

Bob noted, “On the technical side, the [controversy] is based on how people want to accomplish 3D. For instance, a lot of people are desiring large TSVs [thru-silicon vias] for relatively thick or large wafers. But there are yield issues – issues of the cost of manufacturing, metal migration, thermal coupling. And, a lot of current equipment is not geared to handle thick wafers.

“However,” he said, “those are specific forms of 3D. There are other forms, like what we practice, where there aren't any fundamental showstoppers. They're both currently manufacturable and reliable.

“There is a large problem today, however, between the tool vendors, the customers, and the fabs, in that the fabs only see 3D as a target technology at 45 nanometers and below. Certainly that's what the customers are saying, but the bigger problem is that the tool vendors haven't produced any tools yet.

“I'm also sure that nobody's produced anything in 3D below 90 nanometers, so there's actually no proven existence at smaller geometries, which ironically is where most people think it's needed the most. But, you're not going to get a large company doing a 100-million unit program at 28 nanometers in 3D, for instance, without the technology first being proven. So, everybody’s sitting at the table and nodding that 3D is the right answer [to solving the scaling issues], but nobody knows how to get started.

“And that, in a nutshell, is the principle problem with 3D.”


It's Just Business ...

I asked Bob how the business issues related to 3D get resolved? He answered, “As we see it, we're doing MPW runs at 130 nanometers, doing runs at 130 and 100 nanometers with other stuff, and working at other nodes not even worth mentioning, as well.

“We've had dozens of customers that are doing early design studies, trying to get some sort of flow worked out, but very few of those parts are going to go into anything resembling high-volume production. So, it's a lot about building up confidence in the technology. A fair number of parts will go into low-volume production – runs in the thousands to tens of thousands – and some might get into the low millions of parts, but this is only a stepping stone.

“The truth is, you need to start with some easier designs that are within the capability of the tools as they exist today, and a problem of the appropriate scale that doesn't force the company to bet their existence on an untried technology.

“I don't foresee Intel, for instance, announcing a 3D processor within the next several years without first [mastering] stacked memories, and then selling those memories in servers. It's just got to be an evolution into the high-volume marketplace. We are particularly seeing this [strategy] among the larger technology companies, where they're concentrating on some sort of niche market.”

I stopped Bob: If the technology's just not that tough, then why don't big companies go forward with their 3D initiatives, Intel included?

He answered my question with a question: “What does it buy them? The best way [to utilize 3D] is to have lots of memory on top of the processor, which means Intel has to partner with – or be in – the memory business. They're not there yet, but never say never.

“Of course, there's also a lot of conservatism in the large companies with respect to 3D, because it's still today seen as being revolutionary – changing a lot of things all at once.

“You're changing the design, the supply chain, the fabrication processors, and so on, so any conservative business person would simply ask, Why? Why change all of these elements without first proving that you’re getting your product [out the door] cheaper, faster, and with better power characteristics.

“Many years ago, we told a senior executive at one of the large DRAM companies that 3D could do everything. He said, 'I'm willing to believe that what you say is true, but [to do 3D] I'll have to change how I design, test, and process in the fabs – and all at the same time – in order to realize any benefits from what you're offering. If I could change just one of those things and achieve incremental improvements, we could possibly go down this road. But you're asking too much of us to do it all at once, asking us to assume too much risk.'”

Bob noted, “That was actually 8 years ago, and we're still seeing a lot of that type of attitude today!”


3D vs. The Big Bad Shrink ...

Consider the cost of process shrink. Bob said, “It used to be when we did a shrink – say, 10 years ago – we got more transistors at a lower cost, used less power, and [the device] ran faster. But somewhere around 110 nanometers, plus or minus, things no longer ran any faster – although they were still cheaper and used less power.

“Then at 45 nanometers, we woke up one day and found it wasn't any faster and used no less power, but it was still cheaper. And now, we're on the verge of waking up and and discovering that there's no reason at all to make it smaller. It's not faster, uses no less power, and isn't even cheaper. Yes, the technology [to do the smaller geometries may exist], but there's no cost benefit.

“Now the fabs are facing issues at 28 nanometers, and 16 nanometers is even more daunting. It's all incredibly expensive, and nobody yet knows if 28 nanometers is even going to cost less than 45 nanometers. Yet the industry depends on moving forward the technology to give consumers more and more. We're rapidly approaching a point where we might be able, technically, to build something, but there will be no business case for doing so.

“This is why we're actually reaching the point where the industry will simply adopt 3D – which, by the way, will also do great things for the 450 millimeter wafer crowd. They won't see all the advantages of those wafer sizes until we go 3D, but when we do, it will be significant!”


The Missing Links ...

As I cover the EDA industry, I asked Bob what he believes is missing in the tools today with respect to designing 3D. He said, “We've strung together a fairly good back-end flow. If you're building things today that are a regular structure and not very complicated – big memories with lots of transistors – you can use existing tools to produce parts.

“However, for more complex design, there are huge pieces missing. Synthesis, place & route, and certainly the path-finding tools – these are all highly desirable, and all missing.

“The biggest problem is that there aren't a lot of choices. When you do 2D chip design, you know if you put in an embedded DRAM it will cost you X amount more. If you're going to put in mixed signal, you've got to design it a certain way to make it cost effective.

“With 3D in the the wafer, however, and working to different fabs – you can mix and match in such a wide variety of ways, the number of permutations is so great, it's almost impossible to figure out what doable. Calculating the cost-effectiveness of your various choices is totally daunting – especially among the high-volume manufacturers.

“The path-finding tool needs a lot of growth and enhancement. The place & route tools are okay; the routing's simple, it's what to do with the TSVs that's the issue. And, depending on when you're putting these together, you may find problems with trapped heat and thermal issues. Although that's not necessarily a problem with all 3D.

“Clearly, they really need [some sort of ROI tool] that will justify that 100-million-dollar investment needed to bring 3D up to speed. You can't just do it with a couple of guys sitting around a table talking about the trade-offs. It will be a blend of what the tool says you should do, and what the guys with the coffee cups say you should do.”


The Holy Grail ...

Bob went on, “What I hear from a lot of large IDM players is that they really want to be able to write a bunch of Verilog code and put it into the next-generation tool, for instance. They want that tool to spit out a 45-nanometer netlist, and at 65- and 28-nanometers, and to be able to partition the circuity up to take advantage of the trade-offs in size, cost, and speed. We are, however, a long away from that tool actually existing.

“Certainly a lot of tool vendors understand what they need to do, but they also look at it from the standpoint of talking to their customers and finding out what they need today. If those customers aren't sure about which 3D they're going to be using and at what process node, plus aren't sure how they're going to assemble [things], the vendor has difficulty [working to the customer's specifications].

“So, it obscures the direction that the tool guy needs to go. They can't get a clear picture of what they need to do to satisfy the customer's needs, and they certainly don't want to be providing tools for all types of 3D at all process nodes. Again, we hear a similar message from the tool vendors, 'We're only willing to build a tool if someone's willing to buy it.'

“Again, you need to have the EDA vendors, the customers, and the fabs all sitting at the same table, and all agreeing that 3D is the right thing to do. Currently, no single group is prepared to jump off that cliff if they think they're jumping alone.

“With that said, I have had great success with Magma’s tools. I have been using their Quartz DRC for production designs of 3D IC for years now. Magma has responded to a critical next step by developing an excellent 3D LVS solution, as well. Because of the Magma software’s fundamental architecture and its ability to accurately model TSVs with QuickCap, I believe they are poised to emerge as the 3D EDA supplier of choice.”

And, short of jumping off a cliff, what does it actually mean when a fab says they're ramping up to do 3D? Bob answered, “Some fabs have a very specific set of ideas of what they mean when they say 3D, but in general, I'd say it means the fab is preparing to do large vias geared towards the die-to-die solution. Although, many of the people I talk to at fabs are also trying to figure out how to do intimate connections to memory.

“For instance, UMC and Elpida have recently tied up an agreement, and I wouldn't be shocked to see that TSMC and Samsung are tying up a partnership, as well. Fabs have all sorts of cooperative arrangements with memory makers.

“It's a recurring theme for early 3D integrators to take memory off of the logic device to create a separate device. But, the 3D assembly is preferred because of the smaller package and lower bandwidth offering, which appeal to a lot of our customers.

“Clearly there are still some technical problems to be ironed out [in 3D], but everything has evolved considerably in recent years, and continues to improve. I just don't see any showstoppers [to prevent further progress]. There are some issues, as we've all been reading about, but there are certainly no fundamentals at all standing in the way. I don't see anything preventing 3D from entering the market. At Tezzaron, we've built hundreds of thousands of devices and have had enough practical yield with moderate volume to know this to be a certainty. ”


Expect More in 2011 ...

So, will we be hearing about revolution, or evolution, with respect to 3D next year at DAC 2011?

Bob answered by referencing his recent role as a reviewer for an IEEE conference in Germany: “There's starting to be a fair number of papers coming in – people are building real things [with 3D technology] and showing tangible results. You can see it in the various papers I'm reviewing.

“Currently, there are 70 or more people doing various things in 3D, with probably a quarter of those at universities. People are beginning to publish their results. They're doing it. They're doing 3D. And as people see more and more proof of the success of 3D, more and more people will try things – and then publishing more results to show that it works.

“This process is going to cause the decision makers in the various companies to look at 3D, and to say, 'So and So at Whatever University was able to do this, and presented it, so certainly we should be able to do this as well.'

“The conference papers, therefore, end up being very important. They give the industry a level of confidence that would not otherwise be there. Plus, there's the obvious point that if university people with less funding can do it, then we as an industry can do it.”

Bob concluded, “But, there isn't going to be a revolution. We're going to see an evolution of attitude about what we can do in 3D, and the perception of [associated] risk.

“As that perception of the risk goes down radically, it will be seen that it's much safer to do 3D [in the long run] than to try to migrate down to 16 nanometers.”


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