* Agilent Technologies announced Update 3 release of its Advanced Design System (ADS) high-frequency EDA software. The company says the new release includes the "addition of SERDES/Verilog analog mixed-signal (AMS) co-simulation, and other signal integrity capabilities."

Sanjeev Gupta, Product Marketing Manager at the company, is quoted: "The ability to co-simulate and use SERDES models in ADS along with digital components lets designers simulate serial links from end to end, and helps ensure that the analog and digital parts of their circuit will work together and behave as expected."

* Altera announced its Plug & Play Signal Integrity technology, which the company says "redefines FPGA use in high-performance systems by enabling a single card configuration to be plugged into any designated system slot while under system power … [The] technology is an exclusive combination of low-power linear adaptive equalization technology – Altera's new Adaptive Dispersion Compensation Engine (ADCE) – and the hot-socketing capability found in every Altera FPGA. When hot-swapping a single card configuration in a system, the ADCE automatically monitors and adjusts itself for interconnect loss and environmental variations to provide the highest system performance and data reliability available in the industry today."

* Apache Design Solutions announced that MediaTek selected Apache as their "EDA partner for addressing 65- and 45-nanometer physical design challenges." The companies say the collaboration will focus on areas of power and noise -- power signoff, advanced low power and leakage optimization, reliability methodology, thermal integrity, and IC-package noise management.

* Apache also announced that Toshiba has standardized on Apache's RedHawk for power signoff of their 90- and 65-nanometer designs. Tamotsu Hiwatashi, Senior Manager, System LSI Design Department, System LSI Division at Toshiba, is quoted: "Apache's support has been outstanding, not only in their technical expertise, but also in their responsiveness to meet our needs, which has enabled us to increase confidence in the quality of our designs."

* ARC and Cadence Design Systems announced "a new automated Common Power Format (CPF)-enabled low-power reference design methodology (LP-RDM) has been implemented in ARChitect, ARC's patented processor configuration tool. This LP-RDM together with the Cadence Low Power Solution ensures that ARC's new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power."

* Berkeley Design Automation and Matsushita Electric Industrial Co., Ltd. announced a partnership for analog/RF and mixed-signal design verification for Matsushita's Digital-RF Chip Design Platform. Per the Press Release: "The partnership is based on the technology from Berkeley Design Automation's Analog FastSPICE and RF FastSPICE tools."

* Cadence Design Systems (India) Pvt. Ltd., the Indian subsidiary of Cadence Design Systems, Inc. announced that RFIC Solutions, Inc. "increased productivity two-fold by adopting the Cadence Virtuoso custom design platform … RFIC Solutions successfully completed two tapeouts within the first month of adopting the Cadence technology."

* CoWare announced a collaboration with STMicroelectronics to create "an advanced ESL design automation environment based on CoWare's Processor Designer and CORXpert Personalization Kit for STMicroelectronics custom processors."

Philippe Galliard, Software Tools Development Manager, Software Tools and Services Division at ST, is quoted: "This process is handled securely by the CORXpert software and frees up the engineers so that they can concentrate on optimizing cores rather than being trapped in the manual operation that was previously required. By taking advantage of the shorter development cycles, ST engineers can target the entire application range, from dedicated controls to complex applications in the multi-media domain, with cost, performance, and power optimized custom processors."

* EMA Design Automation and AEi Systems announced version 2.0b of AEi Systems' Power IC Model Library for the Cadence PSpice simulator. The companies say, "Version 2.0b has over 200 time-domain simulation models for power electronic designs. Several previously unavailable Texas Instruments models debut in version 2.0b, and future updates are anticipated to focus on many of TI's newest and most popular components … The Power IC Model Library includes model netlists in PSpice syntax, schematic symbols for both Cadence OrCAD Capture and legacy schematics, and a set of example application circuits for many of the IC models."

Manny Marcano, President & CEO at EMA, says the news is good: "The Power IC Model Library for PSpice contains parts that are simply not available from any other EDA company. AEi Systems has proprietary relationships with nearly all of the top analog IC manufacturers -- relationships that provide unique access to the part characteristics needed to produce models with the accuracy our customers expect."

* EVE announced that Tensilica used EVE's ZeBu to validate the Diamond 38xVDO Video Engines. Beatrice Fu, Senior VP of Engineering at Tensilica, is quoted: "ZeBu allowed us to validate changing codec and hardware revisions almost immediately. The result was a high confidence that our final product, really a combination of hardware and software, would just work."

* Dongbu HiTek announced a new design library that supports CMOS Image Sensor (CIS) processing at the 110-nanometer node. The company says the new library enables low leakage current in standby status as well as up to 5-megapixel resolution in camera phones.

* Fujitsu Ltd. and Denali Software announced their co-development of a DDR DRAM physical interface (DDR PHY) product compatible with the recently announced DDR-PHY Interface (DFI) version 1.0 specification. The companies say the "DDR PHY utilizes the DFI specification, which defines a common interface between the conventional proprietary memory controller logic and DDR PHY designs."

* IMEC announced its ultra-low power (0.7 mW), high-speed (50MSamples/s) ADC achieved a figure of merit of 65fJ per conversion step. Per the Press Release: "This is 2.5 times better than the best ADC of this kind ever reported in research papers and an order of magnitude better than the best commercially available ADC IP blocks in 90-nanometer CMOS. The novel IMEC SAR ADC design is especially suited for nomadic applications in the IT realm. Its power scales linearly with the clock rate over a very wide range which makes it very well suited for software-defined radio applications. It is implemented in pure digital CMOS technology, making it very well suited for scaling to the 45-nanometer CMOS node and below. The design is available as 'white box IP' for transfer to the industry."

* LogicVision announced Silicon Insight, which the company describes as "a new desktop silicon diagnostic solution, [which runs] on a Linux PC or laptop [and] interfaces to a customer's device or performance board through simple USB-to- JTAG cable interface hardware to provide an interactive graphical environment for characterization, debug and diagnosis of silicon devices incorporating LogicVision's embedded test IP. With Silicon Insight it is now possible to perform full device debug and diagnostics without the need to access or tie-up expensive automatic test equipment." Expect more discussion at ITC in October.

Adrian Arozqueta, DFT Manager at PLX Technology, is quoted in the Press Release: "By using LogicVision's Silicon Insight product, PLX was able to easily characterize an embedded RAM in one of our latest devices. In addition to the advantages in cost and convenience of performing device diagnostics in the lab as opposed to on the production floor, we were able to complete the characterization of the RAM across multiple operating conditions and process corners within hours of the software installation."

* Mentor Graphics announced the PADS I/O Designer for the PADS product user community. Henry Potts, VP and GM of Mentors' Systems Design Division, is quoted: "Users of high-end FPGAs report time-to-market reduction and systems performance improvement of up to 50 percent, and reductions in PCB layer counts resulting in reduced product costs. With the continuing trend in electronic products of using even more high-end FPGAs, the impact of providing I/O Designer to our PADS users is significant."

* Mentor also announced that MediaTek is using Mentor’s 0-In Formal Verification technology for MediaTek’s functional verification methodology. Per the Press Release: "MediaTek’s complex multimedia designs require thorough verification at the RTL level to confirm interface compliance and the functionality of control logic. MediaTek uses the 0-In Formal Verification technology for bug hunting, which is the process of pinpointing errors during functional verification and analyzing assertions that focus on verification hot spots."

* MIPS Technologies announced that Opulan Technologies has "extended its commitment" to MIPS architecture and cores, and is using the MIPS32 4KEc hard IP core for its next-generation broadband-access SoC designs. Per the Press Release: "Developed by MIPS Technologies' Shanghai R&D facility and targeting TSMC's 130-nanometer process, the 4KEc hard core is a technology-specific implementation of the synthesizable 32-bit 4KEc processor. Opulan is the latest China licensee to develop MIPS-Verified designs, further establishing Greater China as MIPS' fastest growth market worldwide."

* Nikon and Synopsys announced that Nikon's optical lithography exposure tool data is included in the latest release of Synopsys’ Proteus OPC software. Per the Press Release: "As part of an ongoing collaboration, the two companies developed an embedded scanner parameter module, which delivers the manufacturing-aware OPC and RET lithography simulation models needed for 45-nanometer and below IC manufacturing … The newly developed interface allows Proteus modeling customers to automatically access Nikon's proprietary scanner information, including such higher-order lithographic effects as polarization, flare, synchronization, and various aberration data."

* Parasoft Corp. announced extended support for its C/C++ tool, Parasoft C++test. Sergei Sokolov, Professional Services Manager at the company, is quoted: "Parasoft C++test integrates multiple technologies, enabling developers to start verifying code as soon as it is completed – even if the target hardware is not yet built or available for testing."

* Pulsic Ltd. announced a patent from the U.S. PTO for Pulsic’s spine-and-stitch routing technology, "Method of automatic shape-based routing of interconnects in spines for integrated circuit design." The company says the technology optimizes the layout of long aspect ratio nets found in memory design and "automates a previously manual process."

Also per the Press Release: "Spine and Stitch is a linear routing style used to connect custom cells placed in channels or spine areas of memory. These routing areas are often found in the layout of peripheral logic for DRAM, SRAM and Flash memory, and are characterized by extreme aspect ratios, producing long and narrow routing footprints. The spines are very long and the stitches are shorter orthogonal tracks, which gridded routers are unable to guarantee

* S3 (Silicon & Software Systems) announced the availability of silicon results for its portfolio of high-performance, mixed-signal converter IP at the 65-nanometer technology node. Mike Murray, S3 General Manager, Mixed Signal IP, is quoted: "We have a deliberate strategy to address the needs of the high growth consumer applications market by broadening our IP portfolio at the 90 nanometers, 65 nanometers, and lower technology nodes. S3's first time success in migrating this high performance mixed signal converter IP portfolio to the 65nm node marks another industry first for S3 at this node."

* Solido Design Automation announced new software, SolidoSTAT, designed to address the problem of preventable parametric yield loss for transistor-level statistical design and verification. The SolidoSTAT suite includes 5 tools: SolidoSTAT Sampler accelerates traditional Monte Carlo analysis through parallel processing and high-efficiency sampling algorithms. SolidoSTAT Characterizer pinpoints sources of yield and performance loss in the design. SolidoSTAT Circuit Enhancer automatically explores sizing alternatives. SolidoSTAT Tradeoff Analyzer mines Sampler results, without additional simulations, to identify tradeoffs between specifications that improve yield. SolidoSTAT Visualizer converts raw data from all the analyses into dynamic visual representations."

* Synopsys announced that Global Unichip Corp. is using Synopsys' TetraMAX to improve chip test quality. Louis Lin, Senior Director of Design Service at GUC, is quoted: "As our design complexity increased and our manufacturing process shifted to 90- and 65-nanometers, delay testing became mandatory to enhance test coverage. By adopting the TetraMAX at-speed test solution, we improved test quality for several projects. In addition, we used DFT MAX scan compression to reduce test data volume by more than 90 percent on several designs, and the compressed patterns were later successfully applied on our testers to verify working silicon. It was easy to get DFT MAX working with little impact on our delivery schedules and we are impressed with the test results."

* Synopsys also announced its DesignWare System-Level Library. Some of the details: "The library provides high-performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare Cores and ARM AMBA interconnect components. All DesignWare System-Level Library models are written in SystemC and work in IEEE 1666 (SystemC) compliant simulation environments … The DesignWare System-Level Library features more than 50 TLMs."

* In related news, Synopsys also announced its DesignWare USB 2.0 nanoPHY IP has received USB logo certification, and its PCI Express (PCIe) PHY IP passed compliance testing when implemented in SMIC's 130-nanometer G process technology.

* Finally, Synopsys and Signal Integrity Software, Inc. (SiSoft) announced integration of SiSoft's Quantum-SI tool and Synopsys' HSPICE simulation tool. Todd Westerhoff, VP of Software Products at SiSoft, is quoted: "Quantum-SI extends HSPICE to provide a comprehensive design and analysis environment for pre- and post-route analysis that allows customers to seamlessly mix IBIS and transistor-level models."

* The MathWorks introduced RF Blockset 2, which the company says "extends Simulink with a library of blocks to model the behavior of linear and nonlinear RF components – filters, transmission lines, amplifiers, and mixers – by supporting the widespread Agilent standards for large signal-scattering parameters in system-level verification models." The take-away here is that there are a boatload of standard data file formats for network parameters and noise properties, and RF Blockset 2 helps engineers deal with that nightmare.

* Takumi Technology Corp. says it’s collaborating with Chartered Semiconductor Manufacturing to validate Takumi's Enhance DFM optimization software on Chartered's 65-nanometer implementation of Common Platform technology. Henry Law, VP of Design Services Division at Chartered, is optimistic: "Chartered is encouraged by our early, collaborative results with Takumi, and its potential direct benefit to customers from improved variation control to reduced violations, helping them to better meet their time-to-market windows."

* Voltaire Ltd. and Synopsys, Inc. announced they’re developing a high-performance compute (HPC) cluster for semiconductor mask data-preparation (MDP) applications.

Per the Press Release: "The HPC solution, which consists of the Synopsys CATS MDP solution running on a high-performance compute infrastructure with Voltaire InfiniBand and DataDirect Networks' storage, reduced MDP turnaround time by up to 4X compared to clusters using Gigabit Ethernet … Originally developed for Synopsys’ in-house testing and now available to customers, the new HPC solution delivers high-performance file I/O using the Lustre parallel file system from Cluster File Systems (CFS), DataDirect Networks' S2A (Silicon Storage Appliance) and the Voltaire Grid Director 10 Gigabits/second InfiniBand switches, which use Mellanox Technologies' InfiniBand silicon solutions."

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